The present invention relates to the art of random access memories. It finds particular application in connection the testing of large scale memories and will be described with particular reference thereto. It is to be appreciated, however, that the invention will also find uses in other applications of electronic memories.
A significant amount of work has been done in the recent years to obtain fast and very large memory systems. As a result, the density of semiconductor memory chips has increased dramatically. The increase in density and size of the memories has resulted in a corresponding increase in the difficulty of testing of such memories. A multi-mega bit random access memory (RAM) requires extended amounts of time in order to test cell stuck-at faults and other varieties of possible faults. To overcome this problem, two general approaches have been developed. First, researchers have attempted to develop efficient test generation methods, and second, memories including built-in self-testing capabilities have been proposed.
Several innovative test methods for random access memories have been reported. These methods can be categorized into two classes. One set of methods are based on a stuck-at fault model. Representative examples of proposed methods based on this model include, J. Knaizuk and C. R. P. Hartman, "An optimal method for testing stuck-at faults in ransom access memories", IEEE Trans. Comp., vol. 26(11) , pp. 1141-1144, November 1977; R. Nair, S. M. Thatte and J. A. Abraham, "Efficient methods for testing semiconductor random access memories", IEEE Trans. Comp., vol. 27(6), pp. 572-576, June 1978; R. Nair, "Comments on an optimal method for testing stuck-at faults in random access memories", IEEE Trans. Comp., vol. 28(3) , pp. 258-261, March 1979; R. Dekker, F. Beenker and L. Thijssen, "A realistic fault model and test method for static random access memories", IEEE Trans. CAD, vol. 9(6), pp. 567-572, June 1990; R. Dekker, F. Beenker and L. Thijssen, "Fault modeling and test method development for static random access memories", Proc. Int. Pest Conf., pp. 343-352, 1988; A. Birolini, W. Buchel and D. Heavner, "Test and screening strategies for large memories", Proc. European Test Conf., pp. 276-283, 1989; T. Fuja, C. Heegard and R. Goodman, "Linear sum codes for random access memories", IEEE Trans. Comp. , vol 37(9) , pp. 1030-1042, September 1988; C. A. Papachristou and N. B. Sahgal, "An improved method for detecting functional faults in semiconductor random access memories", IEEE Trans. Comp., vol. 34(2), pp. 110-116, February 1975; J. Savir, W. H. McAnney and S. R. Vecchio, "Fault propagation through embedded multiport memories", IEEE Trans. Comp., vol. 36(5), pp. 592-602, May 1987; R. David, A. Fuentes and B. Courtois, "Random pattern testing versus deterministic testing of RAMs", IEEE Trans. Comp. , vol. 38(5), pp. 637-650, May 1989.
The second class of test methods are based on a pattern sensitive neighborhood cell fault model. Representative examples of these types of methods include, J. P. Hayes, "Detection of pattern sensitive faults in random access memories", IEEE Trans. Comp., vol. 24(2), pp. 150-157, February 1975; J. P. Hayes, "Testing memories for single cell pattern sensitive faults", IEEE Trans. Comp., vol 29(3), pp. 249-254, March 1980; D. S. Suk and S. M. Reddy, "A march test for functional faults in semiconductor random access memories", IEEE Trails. Comp., vol. 30(12), pp. 982-985, December 1981; S. C. Seth and K. Narayanaswamy, "A graph model for pattern sensitive faults in random access memories", IEEE Trans. Comp., vol 30(12), pp. 973-977, December 1981; P. D. Jong and A. V. D. Goor, "Test pattern generation for API faults in RAM", IEEE Trans. Comp., vol. 37(11), pp. 1426-1428, November 1988; P. Mazumder and J. K. Patel, "Parallel testing for pattern sensitive faults in semiconductor random access memories", IEEE Trans. Comp., vol. 38(3), pp. 394-407, March 1989.
The best known methods from both categories are polynomial in time. As the density of memories is quadrupling in every 2-3 years, even a linear increase in test time becomes undesirable for large memories.
To overcome the problem of excessively large test time, built-in self-test (BIST) devices and methods have been developed. These BIST methods can also be categorized into two classes. One set uses extra hardware for on chip test generation and response evaluation (using a parallel signature analyzer). Examples of this category of testing can be found in P. Mazumder, J. H. Patel and J. A. Abraham, "A reconfigurable parallel signature analyzer for concurrent error correction in DRAM", IEEE J. Solid State Circuits, vol. 25(3), pp. 866-870, June 1990; T. Sridhar, "A new parallel test approach for large memories", IEEE Design and Test, pp. 15-22, August 1986; S. K. Jain and C. E. Stroud, "Built-in self testing of embedded memories", IEEE Design and Test, pp. 27-37, October 1986; K. Kinoshita and K. K. Saluja, "Built-in testing of memory using an on-chip compact testing scheme", IEEE Trans. Comp., vol. 35(10), pp. 862-870, October 1986; M. Franklin, K. K. Saluja and K. Kinoshita, "A built-in self-test method for row-column pattern sensitive faults in RAMs", IEEE J. Solid State Circuits, vol. 25(2), pp. 514-523, April 1990.
This class of testing is based on the pattern sensitive neighborhood cell fault model as discussed, for example, in the above Hayes reference.
The second category of testing uses extra hardware to partition the entire memory into small blocks in order to test the blocks in parallel (using external test generation). Examples representative of this form of testing can be found in R. Kraus, O. Kowarik, K. Hoffmann and D. Oberle, "Design for test of Mbit DRAMs", Proc. Int. Test Conf. , pp. 316-321, 1989; P. H. Bardell and W. H. McAnney, "Built-in test for RAMs" IEEE Design and Test, pp. 29-36, August 1988; N. T. Jarwala and D. K. Pradhan, "TRAM: A design methodology for high performance, easily testable, multimegabit RAMs", IEEE Trans. Comp., vol. 37(10), pp. 1235-1250, October 1988; H. McAdams, J. H. Neal, B. Hollard, S. Inoue, W. K. Lob and K. Poteet, "A 1-Mbit CMOS dynamic RAM with design for test functions", IEEE J. Solid State Circuits, vol. 21(5), pp. 635-641, October 1986; P. Mazumder, "Parallel testing of parametric faults in a three dimensional dynamic random access memory", IEEE J. Solid State Circuit, vol. 23(4), pp. 933-941, August 1988; T. Oshsawa, T. Furuyama, Y. Watanabe, H. Tanaka, N. Kushiyama, K. Tsuchida, Y. Nagahama, S. Yamano, T. Tanaka, S. Shinozaki and K. Natori, "A 60 -ns 4-Mbit CMOS DRAM with built-in self test function", IEEE J. Solid State Circuits, vol. 22(5), October 1987; P. H. Voss, L. C. M. G. Pfennings, C. G. Phelan, C. M. O'Connell, T. H. Davies, H. Ontrop, S. A. Bell and R. H. W. Salters, "A 14-ns 256K.times.1 CMOS SRAM with multiple test modes", IEEE J. Solid State Circuits, vol. 24(4), pp. 874-880, August 1989; Y. Matsuda, K. Arimoto, M. Tsukude, T. Oishi and K. Fujishima, "A new array architecture for parallel testing in VLSI memories", Proc. Int. Test Conf., pp. 322-326, 1989.
This class of testing is based upon the cell stuck-at fault model described in the Nair-Thatte-Abraham references previously discussed. The previously mentioned paper, "TRAM: A design methodology for high performance, easily testable, multimegabit RAM's" discloses that use of partitioning methods results in a significant savings the test time required for large memories. The major disadvantage of such partitioning methods is the requirement of large additional hardware overhead. In that paper, it is noted that if a 1M-bit memory is partitioned into 16 blocks (64K-bit modules) using an H-tree, the percentage increase in area due to the additional hardware is approximately 30% of the chip. The hardware overhead decreases the manufacturing yield significantly as well as causes performance degradation.
The general method to test a memory system is to assume a fault model and generate input vectors to cover the faults.
Probably, the most widely used fault model for RAM devices is the stuck-at model as described in the Nair-Thatte-Abraham reference. In the Nair-Thatte-Abraham reference, the entire circuit is divided into three blocks, i.e., memory cell array, decoder circuit and the sense amplifier or read/write circuit. It was considered there that in the memory array, a cell may have stuck-at-1/0 fault or a cell may have a coupling fault with other cells. Any failure in the decoder circuit will result in the address cell not being accessed, a non-addressed cell being accessed, or in multiple cells being accessed. Read/write circuits may have stuck-at-1/0 faults which appear as memory cell stuck-at faults.
Physical fault mechanisms in memory devices have been investigated as shown for example in the above mentioned Dekker-Beenker-Thijssen article. It was found that all the faults in memory can be covered by the fault model given in Nair-Thatte-Abraham, with the addition of state transition faults and data retention faults. A more general fault model will thus include the following faults;
1. Memory cell stuck-at-1/0 fault; PA1 2. Memory cell state transition 1-to-0 and 0-to-1 fault; PA1 3. Memory cell bridging with other cell (state coupling); PA1 4. Stuck-at, multiple access or wrong addressing faults in decoder; and, PA1 5. Data retention fault.
For simplicity, the present discussion is restricted to the above mentioned faults. Also, in this discussion, a single fault assumption has been made. If necessary, one can further extend this fault model by considering transistor stuck-open/stuck-on faults. However, in that case appropriate changes in the test generation method will be required. A simplified fault model may also be used if desired. Any test generation method can be used so long as the test vectors cover all faults under the assumed fault model.